In accordance with recent technical developments, various types of personal computers (PCs), such as desktop computers for use in offices and battery-operated notebook computers for use in mobile environments, have been generated and are available on the market.
A basic configuration for these computer systems includes a CPU, which functions as a central controller, and a main memory, to which the CPU accesses. The CPU executes programs loaded on the main memory, and sequentially writes the results obtained by program execution into work areas in banks of the main memory so that the computer processing is performed.
For the main memory, DRAM (dynamic RAM) is generally used because DRAM has a simple cell structure and increasing the capacity of memory composed of DRAM is easier than increasing the capacity of memory composed of SRAM (static RAM), and also because the cost per DRAM memory capacity is generally less than that of SRAM. The DRAM memory cells in the memory are arranged as a matrix. In order to address memory cells individually, first, row addresses and row address strobe (RAS) signals are supplied, and then, column addresses and column address strobe (CAS) signals are supplied.
In the DRAM memory cells, data are capacitively accumulated and stored as individual electric charges. Thus, when data are written to the memory cells and are left for an extended period of time, the charges leak and the stored data are lost. To prevent such data loss, the written data should be refreshed (i.e., re-written) at a predetermined time intervals. A basic refresh operation consists of the accessing to a specific memory cell row to refresh all of the cells along that row. In order to refresh all of the row addresses, a refresh address counter is required that designates refresh addresses sequentially, and means for providing a refresh cycle, or for issuing a refresh request at a predetermined period of time. It should be noted that, in general, a refresh address counter is so designed that it automatically increments a count value upon each refresh cycle.
The following explanation is with regard to RAS-only refresh and CAS-before-RAS refresh. The refresh control methods are, for example, a "RAS-only refresh" method and a "CAS-before-RAS refresh" method. The RAS-only refresh method is one where a refresh operation is controlled by using only row address strobe (RAS) signals. For this method, a refresh address counter that designates refresh row addresses must be provided outside the memory.
The CAS-before-RAS refresh method is one where a refresh request is supplied to the memory by activating a row address strobe (RAS) signal immediately after the transmission of a column address strobe (CAS) signal, i.e., by using the form CAS-before-RAS. Since an RAS signal is always activated first during a common memory access operation, CAS-before-RAS refreshing is possible. According to this method, so long as a refresh address counter is provided inside the memory, refreshing is performed substantially the same as it is by the RAS-only refresh method. In addition, an external address counter is not necessary. Recent DRAM products that have a memory capacity of 256K bits or larger generally include the CAS-before-RAS function.
The following explanation is with regard to normal refreshing and self-refreshing. From the view point of operational methods, a refresh control operation can be classified as either a "normal refresh" or "self-refresh" operation. A normal refresh operation, as is indicated by the words, is an operation performed while a computer system is in a normal operation mode, i.e, between memory accesses by the CPU. Since a normal refresh circuit is so designed that it employs a high processing speed, in accordance with the access operation by the CPU, it tends to require a large amount of power consumption. A normal refresh operation is usually performed once every 15 .mu.sec, with a refresh cycle of 200 to 500 nsec and a power consumption of 100 mA, and the average current used per hour unit is 2 to 5 mA. As this is the power consumed per DRAM chip, and since four to eight DRAM chips are generally mounted in a PC, the total current consumed during a normal refresh operation can be as much as several tens of mA.
On the other hand, self-refreshing has been developed to reduce the current required for refresh operation, and for this operation, the refreshing is performed internally, by a memory device itself. In order to conduct self-refreshing, the memory device requires means for acquiring a refresh cycle at predetermined intervals, and a refresh address counter to designate a refresh address for each refresh cycle.
Since self-refreshing is performed during when the CPU is not accessing to the memory, self-refreshing may be asynchronized with the operation rate of the CPU. The self-refreshing operation requires the use of only a minimum current (200 to 300 .mu.A) at a longer cycle period so that the data loss in each memory cell can be prevented, self-refreshing can save the power consumption. In addition, as self-refreshing can be performed only inside the memory device, devices other than the memory can be powered down so that the power management effect can be expected. Another aspect bearing on the effectiveness of self-refreshing is that, when viewed from outside the memory, DRAM can be employed as SRAM (as pseudo SRAM) that does not need the refresh operation.
Most computer systems, in which memory backups are taken into consideration, have both the normal refresh function and the self-refresh function. FIG. 6 is a schematic diagram illustrating the arrangement of a computer system that has both the normal refresh function and the self-refresh function. A memory device, and a CPU and an I/O device that provides access to it are connected to each other by a bus. Outside the memory device are provided a normal refresh circuit that performs a relatively fast refresh operation while the CPU is accessing to the memory, and a clock that supplies a relatively short interval signal to the normal refresh circuit. Inside the memory device are provided a self-refresh circuit that performs a relatively slow refresh operation, and an internal clock that supplies a relatively long interval signal to the self-refresh circuit. In addition, a switch is provided to select either the normal refresh circuit or the self-refresh circuit for refreshing the memory device.
The recent memory systems have a plurality of memory banks, for each of which a set of RAS and CAS signals is assigned, and most of the memory system can perform a self-refresh operation for each memory bank. The normal refresh circuit need only transmit a control signal to a memory bank using the CAS-before-RAS method to provide a refresh cycle for the memory bank. Inside the memory bank, an incorporated refresh address counter automatically increments an address upon each refresh cycle. Further, the memory system enters self-refresh mode and activates the incorporated self-refresh function and in response to that, both the RAS and CAS input to the memory bank are kept in the active state for a predetermined period of time.
The following explanation is with regard to reduction in power consumed for memory refreshing. For battery-operated notebook computers, a reduction in the power consumed is an urgent matter, and is required to extend the battery duration in mobile environments. The power required by such a computer system for memory refreshing can also not be ignored. And as was hereinbefore described, since self-refreshing requires less power than normal refreshing, the use of self-refreshing is desirable whenever possible.
However, as self-refreshing is performed at slow speed asynchronously with the CPU operation, as hereinbefore presented, memory bank access (including both read and write access) is disabled in the self-refresh mode. For the stability of the operation, a common DRAM chip is so constructed that once the entry to the self-refresh mode has been triggered, recovery of the memory bank to the normal refresh mode can not be started unless the memory bank has completely entered to the self-refresh mode. Therefore, a delay time of about 100 .mu.sec is required for the recovery by the memory bank from the self-refresh mode to the normal refresh mode. When the memory bank is accessed during the recovery period, the transferred data may be damaged or lost, and accordingly, the security of the system operation could be impaired.
Conventionally, therefore, the security of the system operation is regarded as more important than the power management. While a CPU is executing a normal operation, self-refreshing is not conducted and only normal refreshing is performed. More specifically, self-refreshing is employed only during a period wherein the computer system has entered a low power mode, such as a suspended mode, and has completely halted its normal operation. Even when the CPU is accessing only a specific memory bank, the other memory banks that are not being accessed are not switched to the self-refresh mode.